Designation: Based on experience, Looking for Staff Engineer / Manager and Junior Positions Job description Responsible to lead and work on CMOS Layout of Standard cell and I/O libraries Skills / Experience Should have good understanding of CMOS digital layout techniques Should have hands on experience in digital CMOS layout design of standard cells / I/O cells Should have good understanding in DFM and worked in process technologies 65nm and below Should have experience in Layout migration and generation tools - Sagantec and Cadabra Should have good knowledge in trade offs and expertise in generating 'Compact' layouts to meet performance and area requirements Should have experience in debugging DRC. LVS issues independently Should have hands on experience with all relevant backend tools Cadence- Virtuoso layout editor, Mentor - Calibre, Synopsys STAR RC etc. Should be good at scripting Perl and Skill to develop scripts for automation / quality improvement etc. Qualification: B.Tech / M.Tech in Electronics from reputed university




To view links or images in this forum your post count must be 1 or greater. You currently have 0 posts.

__________________
Thank You,
Administrator
TheIndiaJobs.com Forums