ResponsibilitiesWould be responsible for physical design and verification of large SoCs. Should have excellent hands-on experience pertaining to Floorplanning and Power Grid design, Clocktree, Timing and congestion driven Routing and Chip Finishing and physical verification for large SoCs. Should have excellent knowledge of DSM effect analysis ranging from IR Drop, EM, and Cross talk analysis. Knowledge of layout enhancements for DFM compliance desired. Working experience with SoC Encounter, Calibre, Virtuoso, Primetime, VoltageStorm, Celtic is a pre-requisite for the job. Experience in 65nm technology is a plus.8 + years of experience in large VLSI physical design implementation on 90, 80 or 65 nanometer technology. Successful track record of delivering products to production is a must. Understanding of custom Macro blocks such as RAMs, CAMs, high-speed.




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